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1 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice cmos and ttl compatible i/o automatic page write operation: ?1 to 32 bytes in 5ms ?page load timer end of write detection: ?toggle bit ? data data data data data polling ?rdy/ busy busy busy busy busy hardware and software write protection 100,000 program/erase cycles 100 year data retention description the cat28lv65 is a low voltage, low power, cmos parallel eeprom organized as 8k x 8-bits. it requires a simple interface for in-system programming. on-chip address and data latches, self-timed write cycle with auto-clear and v cc power up/down write protection eliminate additional timing and protection hardware. data polling, rdy/ busy and toggle status bit signal the start and end of the self-timed write cycle. additionally, the cat28lv65 features hardware and software write protection. the cat28lv65 is manufactured using catalyst? advanced cmos floating gate technology. it is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. the device is available in jedec approved 28-pin dip, 28-pin tsop, 28-pin soic or 32- pin plcc packages. block diagram features 3.0v to 3.6v supply read access times: ?150/200/250ns low power cmos dissipation: ?active: 8 ma max. ?standby: 100 a max. simple write operation: ?on-chip address and data latches ?self-timed write cycle with auto-clear fast write cycle time: ?5ms max. commercial, industrial and automotive temperature ranges addr. buffer & latches addr. buffer & latches inadvertent write protection control logic timer row decoder column decoder high voltage generator a 5 ? 12 ce oe we a 0 ? 4 i/o 0 ?/o 7 i/o buffers 8,192 x 8 e 2 prom array 32 byte page register v cc data polling, rdy/busy & toggle bit rdy/busy 64k-bit cmos parallel eeprom cat28lv65
cat28lv65 2 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice pin configuration dip package (p, l) tsop top view (8mm x 13.4mm) (h13) soic package (j, w) (k, x) plcc package (n, g) oe a 9 a 8 nc we v cc rdy/busy a 12 a 7 a 6 a 5 a 4 a 3 a 10 ce i/0 7 i/0 6 i/0 5 i/0 4 i/0 3 gnd i/o 1 i/o 0 a 0 a 1 i/o 2 a 2 a 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin functions pin name function pin name function a 0 ? 12 address inputs we write enable i/o 0 ?/o 7 data inputs/outputs v cc 3.0 to 3.6 v supply ce chip enable v ss ground oe output enable nc no connect rdy/ bsy ready/ busy status i/o 2 v ss i/o 6 i/o 5 13 14 20 19 18 17 9 10 11 12 24 23 22 21 a 1 a 0 i/o 0 i/o 1 oe a 10 ce i/o 7 a 5 a 4 a 3 a 2 5 6 7 8 1 2 3 4 rdy/busy a 12 a 7 a 6 a 9 a 11 28 27 26 25 v cc we nc a 8 i/o 4 i/o 3 16 15 a 6 a 5 a 4 a 3 5 6 7 8 a 2 a 1 a 0 nc 9 10 11 12 i/o 0 13 a 8 a 9 a 11 nc 29 28 27 26 oe a 10 ce 25 24 23 22 i/o 7 21 i/o 1 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 14 15 16 17 18 19 20 4321323130 a 7 a 12 rdy/busy nc v cc we nc i/o 6 top view i/o 2 v ss i/o 6 i/o 5 13 14 20 19 18 17 9 10 11 12 24 23 22 21 a 1 a 0 i/o 0 i/o 1 oe a 10 ce i/o 7 a 5 a 4 a 3 a 2 5 6 7 8 1 2 3 4 a 12 a 7 a 6 a 9 a 11 28 27 26 25 v cc we nc a 8 i/o 4 i/o 3 16 15 rdy/busy
cat28lv65 3 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. absolute maximum ratings* temperature under bias ................. ?5 c to +125 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to ground (2) ........... ?.0v to +v cc + 2.0v v cc with respect to ground ............... ?.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (3) ........................ 100 ma reliability characteristics symbol parameter min. max. units test method n end (1) endurance 10 5 cycles/byte mil-std-883, test method 1033 t dr (1) data retention 100 years mil-std-883, test method 1008 v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(4) latch-up 100 ma jedec standard 17 note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) the minimum dc input voltage is ?.5v. during transitions, inputs may undershoot to ?.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (3) output shorted for no more than one second. no more than one output shorted at a time. (4) latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc +1v. mode selection mode ce we oe i/o power read l h l d out active byte write ( we controlled) l h d in active byte write ( ce controlled) l h d in active standby, and write inhibit h x x high-z standby read and write inhibit x h h high-z active capacitance t a = 25 c, f = 1.0 mhz symbol test max. units conditions c i/o (1) input/output capacitance 10 pf v i/o = 0v c in (1) input capacitance 6 pf v in = 0v
cat28lv65 4 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) output floating (high-z) is defined as the state when the external data line is no longer driven by the output buffer. (3) v ihc = v cc ?.3v to v cc +0.3v. d.c. operating characteristics v cc = 3.0v to 3.6v, unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc v cc current (operating, ttl) 8 ma ce = oe = v il , f = 1/t rc min, all i/o? open i sbc (3) v cc current (standby, cmos) 100 a ce = v ihc , all i/o? open i li input leakage current ? 1 av in = gnd to v cc i lo output leakage current ? 5 av out = gnd to v cc , ce = v ih v ih (3) high level input voltage 2 v cc +0.3 v v il low level input voltage ?.3 0.6 v v oh high level output voltage 2 v i oh = ?00 a v ol low level output voltage 0.3 v i ol = 1.0ma v wi write inhibit voltage 2 v 28lv65-15 28lv65-20 28lv65-25 symbol parameter min. max. min. max. min. max. units t rc read cycle time 150 200 250 ns t ce ce access time 150 200 250 ns t aa address access time 150 200 250 ns t oe oe access time 70 80 100 ns t lz (1) ce low to active output 0 0 0 ns t olz (1) oe low to active output 0 0 0 ns t hz (1)(2) ce high to high-z output 50 50 55 ns t ohz (1)(2) oe high to high-z output 50 50 55 ns output hold from t oh (1) address change 0 0 0 ns a.c. characteristics, read cycle v cc = 3.0v to 3.6v, unless otherwise specified.
cat28lv65 5 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice device under test vcc 1.8 k output c l includes jig capacitance c l = 100 pf 1. 3k input pulse levels reference points 2.0 v 0.6 v v - 0.3 v 0.0 v cc figure 1. a.c. testing input/output waveform (4) figure 2. a.c. testing load circuit (example) note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) a write pulse of less than 20ns duration will not initiate a write cycle. (3) a timer of duration t blc max. begins with every low to high transition of we . if allowed to time out, a page or byte write will begin; however a transition from high to low within t blc max. stops the timer. (4) input rise and fall times (10% and 90%) < 10 ns. 28lv65-15 28lv65-20 28lv65-25 symbol parameter min max min max min max units t wc write cycle time 5 5 5 ms t as address setup time0 0 0 0 ns t ah address hold time 100 100 100 ns t cs ce setup time 0 0 0 ns t ch ce hold time 0 0 0 ns t cw (2) ce pulse time 110 150 150 ns t oes oe setup time 0 10 10 ns t oeh oe hold time 0 10 10 ns t wp (2) we pulse width 110 150 150 ns t ds data setup time 60 100 100 ns t dh data hold time 0 0 0 ns t init (1) write inhibit period after power-up 5 10 5 10 5 10 ms t blc (1)(3) byte load cycle time 0.05 100 0.1 100 0.1 100 s t rb we low to rdy/ bus y low 220 220 220 ns a.c. characteristics, write cycle v cc = 3.0v to 3.6v, unless otherwise specified.
cat28lv65 6 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice address ce oe we data out t as data in data valid high-z t cs t ah t ch t wc t oeh t blc t dh t ds t wp rdy/busy t oes t rb high-z high-z address ce oe we t rc data out data valid data valid t ce t oe t oh t aa t ohz t hz v ih high-z t lz t olz byte write a write cycle is executed when both ce and we are low, and oe is high. write cycles can be initiated using either we or ce , with the address input being latched on the falling edge of we or ce , whichever occurs last. data, conversely, is latched on the rising edge of we or ce , whichever occurs first. once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 5 ms. device operation read data stored in the cat28lv65 is transferred to the data bus when we is held high, and both oe and ce are held low. the data bus is set to a high impedance state when either ce or oe goes high. this 2-line control architec- ture can be used to eliminate bus contention in a system environment. figure 4. byte write cycle [we controlled] figure 3. read cycle
cat28lv65 7 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice address ce oe we data out t as data in data valid high-z t ah t wc t oeh t dh t ds t oes t blc t ch t cs t cw rdy/busy t rb high-z high-z page write the page write mode of the cat28lv65 (essentially an extended byte write mode) allows from 1 to 32 bytes of data to be programmed within a single eeprom write cycle. this effectively reduces the byte-write time by a factor of 32. following an initial write operation ( we pulsed low, for t wp , and then high) the page write mode can begin by issuing sequential we pulses, which load the address and data bytes into a 32 byte temporary buffer. the page address where data is to be written, specified by bits a 5 to a 12 , is latched on the last falling edge of we . each byte within the page is defined by address bits a 0 to a 4 (which can be loaded in any order) during the first and subsequent write cycles. each successive byte load cycle must begin within t blc max of the rising edge of the preceding we pulse. there is no page write window limitation as long as we is pulsed low within t blc max . upon completion of the page write sequence, we must stay high a minimum of t blc max for the internal auto- matic program cycle to commence. this programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. a page write will only write data to the locations that were addressed and will not rewrite the entire page. oe ce we address i/o t wp t blc byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 last byte t wc figure 6. page mode write cycle figure 5. byte write cycle [ce controlled]
cat28lv65 8 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice we ce oe i/o 6 t oeh t oe t oes t wc (1) (1) address ce we oe i/o 7 d in = x d out = x d out = x t oe t oeh t wc t oes data data data data data polling data polling is provided to indicate the completion of write cycle. once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on i/o 7 (i/o 0 ?/o 6 are indeterminate) until the programming cycle is com- plete. upon completion of the self-timed write cycle, all i/o? will output true data during a read cycle. toggle bit in addition to the data polling feature, the device offers an additional method for determining the completion of a write cycle. while a write cycle is in progress, reading data from the device will result in i/o 6 toggling between one and zero. however, once the write is complete, i/o 6 stops toggling and valid data can be read from the device. ready/ busy busy busy busy busy (rdy/ busy busy busy busy busy ) the rdy/ busy pin is an open drain output which indicates device status during programming. it is pulled low during the write cycle and released at the end of programming. several devices may be or-tied to the same rdy/ busy line. figure 7. data polling 28lv65 f11 figure 8. toggle bit note: (1) beginning and ending state of i/o 6 is indeterminate.
cat28lv65 9 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice hardware data protection the following is a list of hardware data protection fea- tures that are incorporated into the cat28lv65. (1) v cc sense provides for write protection when v cc falls below 2.0v min. (2) a power on delay mechanism, t init (see ac charac- teristics), provides a 5 to 10 ms delay before a write sequence, after v cc has reached 2.40v min. (3) write inhibit is activated by holding any one of oe low, ce high or we high. (4) noise pulses of less than 20 ns on the we or ce inputs will not result in a write cycle. software data protection the cat28lv65 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. the device is shipped from catalyst with the software protection not enabled (the cat28lv65 is in the standard operating mode). figure 9. write sequence for activating software data protection figure 10. write sequence for deactivating software data protection software data protection activated (12) write data: xx write last byte to last address to any address write data: aa address: 1555 write data: 55 address: 0aaa write data: a0 address: 1555 write data: aa address: 1555 write data: 55 address: 0aaa write data: 80 address: 1555 write data: aa address: 1555 write data: 55 address: 0aaa write data: 20 address: 1555 note: (1) write protection is activated at this point whether or not any more writes are completed. writing to addresses must occur w ithin t blc max., after sdp activation. (1)
cat28lv65 10 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice to activate the software data protection, the device must be sent three write commands to specific addresses with specific data (figure 9). this sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (figure 11). once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. the data protection mechanism is activated until a deactivate sequence is issued regardless of power on/off transi- tions. this gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. to allow the user the ability to program the device with an eeprom programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. the six step algorithm (figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (figure 12 provides reset timing). after the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. figure 11. software data protection timing ce we t wp aa 1555 55 0aaa a0 1555 data address t blc t wc byte or page writes enabled figure 12. resetting software data protection timing ce we aa 1555 55 0aaa data address t wc 80 1555 aa 1555 55 0aaa 20 1555 sdp reset device unprotected
cat28lv65 11 doc. no. md-1024, rev. f ?2008 scillc. all rights reserved. characteristics subject to change without notice ordering information notes: (1) the device used in the above example is a cat28lv65ni-25t (plcc, industrial temperature, 250 ns access time, tape & reel). prefix device # suffix 28lv65 product number cat optional company id n i t tape & reel package p: pdip j: soic (jedec) k: soic (eiaj) n: plcc -25 temperature range blank = commercial (0 ? c to +70 ? c) i = industrial (-40 ? c to +85 ? c) a = automotive (-40 ? to +105 ? c)* speed 15: 150ns 20: 200ns 25: 250ns * -40 ? c to +125 ? c is available upon request l: pdip (lead free, halogen free) w: soic (jedec) (lead free, halogen free) x: soic (eiaj) (lead free, halogen free) g: plcc (lead free, halogen free) h13: tsop (8mmx13.4mm) (lead free, halogen free)
cat28lv65 12 doc. no. md-1024, rev. f ? 2008 scillc. all rights reserved. characteristics subject to change without notice revision history e t a dn o i s i v e rn o i t p i r c s e d 4 0 - r a m - 9 2b s a e r a l l a n i s e g a k c a p n e e r g d e d d a 4 0 - r p a - 0 2c n o i t a n g i s e d t e e h s a t a d e t e l e d n o i t a m r o f n i g n i r e d r o e t a d p u y r o t s i h n o i s i v e r e t a d p u r e b m u n v e r e t a d p u 5 0 - r a m - 9 2d e l c y c e t i r w , s c i t s i r e t c a r a h c c . a e t a d p u 8 0 - t c o - 5 1e . e g a k c a p b p n s ) m m 4 . 3 1 x m m 8 ( p o s t e t a n i m i l e 8 0 - v o n - 8 1f r o t c u d n o c i m e s n o o t t n i r p e n i f d n a o g o l e g n a h c on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any pa rticular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and act ual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a si tuation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center: phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http: //www.onsemi.com/orderlit for additional information, please contact your local sales representative

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